Referring to FIG. 8, a known igniter for an internal combustion engine includes inductive loads (secondary coil 42 and primary coil 45). The igniter uses intermittent sparks that occur in an ignition plug 44 connected to the secondary coil 42 due to high voltages generated across the secondary coil 42 when intermittent currents flow through the primary coil 45 from a power source 41. In this type of igniter, a bipolar transistor has been used as a switching means 43 in the circuit for intermittently flowing current through the primary coil 42. In recent years, however, an insulated-gate bipolar transistor (IGBT) has replaced the bipolar transistor.
A low on-voltage and a low switching loss are important electrical characteristics that the IGBT can satisfy, thus making it suitable for the switching means 43 of the above igniter. To attain a low on-voltage, a punchthrough IGBT having a thin epitaxial layer (n-type drift layer) 26 (see FIG. 7) has been used as the IGBT suitable for the above igniter. Presently, a non-punchthrough (hereinafter abbreviated as NPT) IGBT using an FZ substrate and a field-stop (buffer layer) IGBT, which is expected to attain further improvements in characteristics, are being studied, taking the above electrical characteristics into consideration. The field-stop (hereinafter may be abbreviated as FS) IGBT as mentioned above is a type of punchthrough IGBT. As shown in FIG. 7, which is a sectional view showing the relevant elements, an ordinary punchthrough IGBT is configured so that a semiconductor functional structure, such as a MOS gate structure, is formed in an epitaxial layer 26, which is formed on a low-resistivity semiconductor substrate 25. Requiring the epitaxial layer 26 in the ordinary punchthrough IGBT, however, is costly.
Referring to FIG. 7, a known configuration incorporates a circuit 21 for monitoring the operation status and controlling a gate signal when an abnormality occurs to prevent the IGBT from being destroyed due to overcurrent, overvoltage, or overheating. In the circuit 21, an n-channel MOSFET, formed in a p-well region 9 and whose drain 10-1 is connected to an emitter electrode 3-1 of the IGBT, serves as a main transistor.
In the IGBT incorporating the circuit 21, while the IGBT is ON (i.e., conductive state), holes flow from a collector 1 toward p-well regions 6 (formed on the front surface side) as indicated by an arrow 33 in FIG. 10. This hole current not only serves as a main current of the IGBT, but also flows into the p-type region 9, which is part of the circuit section 21. The hole current (indicated by an arrow 34 in FIG. 10) flowing into the circuit section 21 can cause a parasitic transistor existing in the circuit section 21 to operate. To suppress that, a p-type region (contact p-type region) 8 is formed between the IGBT active section 20 and the circuit section 21 and is short-circuited with the emitter electrode 3-1 through a contact having a large area. A large part of the current flowing into the p-type region 9 is thus diverted to the emitter electrode 3-1, so that only a small amount of current flows into the circuit section 21.
In the L-load igniter circuit, however, when the IGBT transitions from the ON state to the OFF state, the current decreases rapidly so that a rapidly increasing voltage develops across the primary coil 45 in a direction that counters rapid decrease of current i flowing through it, which is represented by L×di/dt (the positive side is the collector side of the IGBT), where L is the inductance of the primary coil 45. When an OFF state has been established, the voltage decreases rapidly. This surge voltage (hundreds of volts) is clamped by a Zener voltage of Zener diodes 16 connected between the collector and gate of the IGBT, with its anode located on the gate side, whereupon a reverse voltage is induced across the secondary coil 42. In the above process, the positive surge voltage on the primary side can turn to a negative voltage (tens of volts to 100 V) as it lowers. If a negative voltage occurs on the primary side, a reverse bias is applied to the collector 1 of the IGBT, in which case the IGBT can be damaged.
This type of IGBT destruction will be described below with reference to FIG. 9. When a negative bias 30 is applied to the collector 1, a pn junction 19 between a collector region 25 and a buffer layer 24 of the IGBT is biased reversely, whereas a pn junction 17 between a drift layer 26 and the p-well regions 6 located on the front surface side of the IGBT is forward-biased. Therefore, when the collector 1 is biased negatively, the breakdown voltage is determined by the pn junction 19. The pn junction 19 is in the form of a flat plane, but the end of the pn junction 19 is exposed in a circumferential cutting face of the chip. Since the chip-shaped IGBTs are cut out mechanically in lattice form from a large-diameter wafer, the peripheral cutting face of each chip can contain many crystal defects (damage). Therefore, in a peripheral cutting face 32 of the collector-side pn junction 19, the reverse breakdown voltage varies widely depending on the position, and a local region where the breakdown voltage is very low can exist. When a negative bias surge is applied, a large current is concentrated in the low-breakdown-voltage local region, making the device prone to damage.
On the other hand, as described above, the punchthrough IGBT is costly because it requires an epitaxial layer. In contrast, using an inexpensive FZ n-type substrate, the NPT-type IGBT, and the FS-type IGBT can be manufactured at a lower cost and can exhibit a low ON-voltage. In this respect, their use as an IGBT of an igniter for an internal combustion engine is being studied.
The above-described problem occurs when a negative bias surge is applied, which makes the device prone to damage because a large current can be concentrated in a low-breakdown-voltage local region, which is particularly vulnerable in the NPT-IGBT and the FS-IGBT. This is because in the NPT-IGBT and the FS-IGBT, the collector region is a very thin layer of about 1 μm and the end of the pn junction 19 is close to the side end of the back surface where chipping most likely would occur. A reverse blocking IGBT, which solves this problem, is known. Here, the end of the pn junction is not exposed in chip cutting faces so that sufficient breakdown resistance to a negative collector voltage is secured. See JP-A-2007-165424.
A reverse conducting IGBT, which employs another method, has been invented. Here, an n-type region, which is given the same potential as the collector, is formed on the front surface side of an IGBT chip and connected to the collector by a bonding wire. See U.S. Pat. No. 5,519,245 (Japanese Patent No. 2,959,127). Many types of reverse conducting IGBTs incorporating a fly-wheeling diode (FWD) have been proposed. See for example, U.S. Pat. No. 4,689,647 (JP-A-61-15370), JP-A-63-209177, JP-A-2-309676, and U.S. Pat. No. 5,360,984 (JP-A-5-152574).
In the reverse blocking IGBT disclosed in JP-A-2007-165424, however, it is necessary to form a deep p-type diffusion region of 100 μm or more. Furthermore, it is also necessary to secure, near the periphery of an IGBT chip, a wide region needed to form the deep diffusion region. These require a very long heat treatment process, for example, which results in very low throughput (production efficiency). Furthermore, high-temperature, long-time heat treatment causes various problems, such as introducing many crystal defects into the silicon semiconductor and lowering the yield to a large extent.
U.S. Pat. No. 5,519,245 is not directed to a measure against a negative collector voltage discussed above, but relates to a technique in which an FWD, which is usually attached externally, is incorporated in an IGBT used in an L-load drive circuit, such as an inverter. In the structure disclosed in U.S. Pat. No. 5,519,245, since a metal electrode given the same potential as the collector is in ohmic contact with the n-type region formed in a peripheral portion adjacent to the emitter-side (positive-potential side) surface, even if a negative collector bias is applied, a large current flows through a p-well region in contact with an emitter electrode. Therefore, almost no voltage drop occurs, the degree of heat generation is low, and no current concentration occurs. It is necessary, however, to form a large-area n-type region in a peripheral portion on the front surface side (emitter side) of a semiconductor chip. This increases the chip size. The reverse conducting IGBTs disclosed in U.S. Pat. No. 4,689,647, JP-A-63-209177, JP-A-2-309676, and U.S. Pat. No. 5,360,984 have similar problems.
Furthermore, as described above, to prevent an abnormal latch-up operation when the IGBT incorporating the circuit section 21 (see FIG. 10) is ON, it is necessary to form a large contact region between the IGBT active section 20 and the circuit section 21. This increases the chip size of the IGBT.
Accordingly, there remains a need for a semiconductor device that avoids the above-mentioned problems. The present invention addresses this need.